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1 40v general purpose precision operational amplifier isl28177 the isl28177 is an op07 replacement featuring low input offset voltage, low input bias current, and competitive noise and ac performance. the esd ratings are best among competitive parts at 5kv hbm, 300v mm, and 2.2kv cdm. the amplifier operates over the 6v (3v) to 40v (20v) range. applications include precision active filters, medical and analytical instrumentation, pr ecision power supply controls, and industrial sensors. the isl28177 is available in the sot23-5 and soic-8 packages and operates over the extended temperature range to -40c to +125c. features ? wide supply range . . . . . . . . . . . . . . . . 6v (3v) to 40v (20v) ? low input offset voltage . . . . . . . . . . . . . . . . . . . . 150v, max ? input bias current . . . . . . . . . . . . . . . . . . . . . . . . . . . .1na, max ? low noise . . . . . . . . . . . . . . . . . . . . . . . . . . .9.5nv/ hz @ 1khz ? gain bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600khz ? exceptional esd performance . . . . . . . . . 5kv hbm, 300v mm, 2.2kv cdm ? operating temperature range. . . . . . . . . . .-40c to +125c ?packages - isl28177 (single) . . . . . . . . . . . . . . . . . . . sot23-5, soic-8 applications ? precision active filters ? medical and analytic al instrumentation ? precision power supply controls ? industrial sensors figure 1. typical application figure 2. input noise performance - + output v + r 1 v - r 2 c 1 c 2 sallen-key low pass filter (10khz) v in 1.84k 4.93k 3.3nf 8.2nf 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o lta g e ( nv / h z ) frequency (hz) i n p u t n o i s e c u r r e n t ( pa / h z ) 1 10 100 1000 10000 1 10 100 1000 10000 v s = 18v input noise current input noise voltage april 5, 2012 fn7859.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl28177 2 fn7859.2 april 5, 2012 ordering information part number (note 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # ISL28177FBZ 28177 fbz -40 to +125 8 ld soic m8.15e ISL28177FBZ-t13 (note 1) 28177 fbz -40 to +125 8 ld soic m8.15e ISL28177FBZ-t7 (note 1) 28177 fbz -40 to +125 8 ld soic m8.15e ISL28177FBZ-t7a (note 1) 28177 fbz -40 to +125 8 ld soic m8.15e coming soon isl28177fhz tbd -40 to +125 sot23-5 p5.064a notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl28177 . for more information on msl please see techbrief tb363 . pin configurations isl28177 (8 ld soic) top view isl28177 (5 ld sot-23) top view pin descriptions isl28177 (8 ld soic) isl28177 (5 ld sot-23) pin name equivalent circuit description 3 3 in+ circuit 1 amplifier non-inverting input 4 2 v- circuit 3 negative power supply 2 4 in- circuit 1 amplifier inverting input 7 5 v+ circuit 3 positive power supply 61v out circuit 2 amplifier output 1, 5, 8 - nc - no internal connection nc in- in+ v - 1 2 3 4 8 7 6 5 nc v+ v out nc + - out v- in+ v+ in- 1 2 3 5 4 circuit 2 circuit 1 v+ v- circuit 3 capacitively coupled esd clamp in- v+ v- in+ 500 ? 500 ? v+ v- out
isl28177 3 fn7859.2 april 5, 2012 absolute maximum ratings thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44v maximum differential input voltage . . . . . . . 44v or v - - 0.5v to v + + 0.5v min/max input voltage . . . . . . . . . . . . . . . . . . 44v or v - - 0.5v to v + + 0.5v min/max input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma output short-circuit duration (1 output at a time) . . . . . . . . . . . . . . indefinite esd ratings human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 5kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 300v charged device model (tested per cdm-22ci0id) . . . . . . . . . . . . . .2.2kv thermal resistance (typical) ja (c/w) jc (c/w) 5 ld sot-23 package (notes 4, 5) . . . . . . . . tbd tbd 8 ld soic package (notes 4, 5) . . . . . . . . . . 125 73 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions ambient operating temperature range . . . . . . . . . . . . . .-40c to +125c maximum operating junction temperature . . . . . . . . . . . . . . . . . .+150c operating voltage range. . . . . . . . . . . . . . . . . . . . . .6v (3v) to 40v (20v) caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. electrical specifications v s = 5v to 15v, r l = open, v cm = 0v, t a = +25c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. parameter description conditions min (note 6) typ max (note 6) unit v os input offset voltage 150 v -40c to +85c 250 v -40c to +125c 350 v tcv os input offset voltage temperature coefficient -40c to +125c 0.5 1.4 v/ c v os /time long term v os stability 0.4 v/mo i b input bias current 0.2 1 na -40c to +125c 1 na i os input offset current 0.2 1 na -40c to +125c 1 na e n input noise voltage f = 0.1hz to 10hz 0.38 v p-p input noise voltage density f = 10hz 13 nv/ hz input noise voltage density f = 100hz 9.6 nv/ hz input noise voltage density f = 1khz 9.5 nv/ hz i n input noise current density f = 1khz 87 fa/ hz v cmir common mode input voltage range guaranteed by cmrr test v - +2 v + -2 v cmrr common mode rejection ratio v cm = v - +2v to v + - 2v 120 140 db 120 db psrr power supply rejection ratio v s = 3v to 20v 115 130 db 115 db v ol output voltage low, v out to v - r l = 2k ? 1.2 1.25 v r l = 2k ? , -40c to +125c 1.3 v v oh output voltage high, v + to v out r l = 2k ? 1.2 1.25 v r l = 2k ? , -40c to +125c 1.3 v sr slew rate r l = 2k ? , c l = 100pf 0.2 v/s gbwp gain bandwidth product r l = 100k ? , c l = 60pf 600 khz avol large signal gain v out = 3v to 13v, r l = 10k ? 120 140 db 120 db
isl28177 4 fn7859.2 april 5, 2012 i s supply current 1.18 1.4 ma 1.7 ma v s supply voltage 3v 20v v i sc short circuit current 30 ma note: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications v s = 5v to 15v, r l = open, v cm = 0v, t a = +25c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter description conditions min (note 6) typ max (note 6) unit typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. figure 3. input offset voltage (v os ) vs temperature figure 4. power supply current (i s ) vs temperature figure 5. positive input bias current (i ib+ ) vs temperature figure 6. nega tive input bias current (i ib- ) vs temperature temperature (c) -40 -20 0 20 40 60 80 100 120 v os ( v ) -100 -80 -60 -40 -20 0 20 40 60 80 100 v s = 15v temperature (c) -40-20 0 20406080100120 i s (ma) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v s = 15v temperature (c) -40-20 0 20406080100120 i bias+ (na) -500 -400 -300 -200 -100 0 100 200 300 400 500 v s = 15v temperature (c) -40-20 0 20406080100120 i bias- (na) -500 -400 -300 -200 -100 0 100 200 300 400 500 v s = 15v
isl28177 5 fn7859.2 april 5, 2012 figure 7. positive output voltage (v oh ) vs temperature figure 8. positive output voltage (v ol ) vs temperature figure 9. positive output voltage (v out ) vs output current (i out ) vs temperature figure 10. unity gain frequency response vs r l figure 11. open loop gain-phase vs frequency fig ure 12. frequency response vs closed loop gain typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) temperature (c) -40-20 0 20406080100120 v oh (v) 13.5 13.6 13.7 13.8 13.9 14.0 14.1 14.2 14.3 14.4 14.5 v s = 15v r l = 2k temperature (c) -40 -20 0 20 40 60 80 100 120 v ol (v) v s = 15v r l = 2k -14.5 -14.4 -14.3 -14.2 -14.1 -14.0 -13.9 -13.8 -13.7 -13.6 -13.5 -15 -10 -5 0 0 1020304050607080 0 5 10 15 v o l ( v ) current (ma) -55c -40c 0c +25c +150c +125c +75c v s = 15v a v = 2 v in = 7.5v-dc r f = r g = 100k v o h (v ) normalized gain (db) frequency (hz) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 10 100 1k 10k 100k 1m 10m r l = 100 c l = 4pf a v = +1 v s = 15v v out = 50mv p-p r l = 499 r l = 1k r l = 10k r l = 100k r l = g a i n ( d b ) , p h a s e ( ) frequency (hz) -40 -20 0 20 40 60 80 100 120 140 160 180 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 100m v s = 15v r l = 1m ? simulation gain phase -10 0 10 20 30 40 50 60 70 g a i n ( d b ) frequency (hz) 10 100 1k 10k 100k 1m 10m a cl = 1 a cl = 10 a cl = 1001 v s = 15v c l = 4pf v out = 50mv p-p r l = open a cl = 101 r f = 0, r g = r f = 100k ? , r g = 100 r f = 100k ? , r g = 1k r f = 100k ? , r g = 11k ?
isl28177 6 fn7859.2 april 5, 2012 figure 13. unity gain frequency response vs c l figure 14. overshoot vs load capacitance figure 15. input noise voltage and current spectral density figure 16. input noise voltage 0.1hz to 10hz figure 17. large signal transient response figure 18. small signal transient response typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) normalized gain (db) frequency (hz) 10 100 1k 10k 100k 1m 10m -10 -8 -6 -4 -2 0 2 4 6 8 r l = 10k a v = +1 v s = 15v v out = 50mv p-p c l = 2200pf c l = 4pf c l = 1000pf c l = 4700pf c l = 10nf c l = 22nf overshoot (%) load capacitance (nf) 0 10 20 30 40 50 60 70 0.001 0.01 0.1 1 10 100 +overshoot -overshoot v s = 15v v out = 50mv p-p r l = 10k a v = 1 0.1 1 10 100 1k 10k 100k input noise voltage (nv/ hz) frequency (hz) i n p u t n o i s e c u r r e n t ( p a / h z ) 1 10 100 1000 10000 1 10 100 1000 10000 v s = 18v input noise current input noise voltage input noise voltage (nv) 012345678910 time (s) -500 -400 -300 -200 -100 0 100 200 300 400 500 v s = 18v a v = 10k v out (v) time (s) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 100 200 300 400 500 600 700 800 900 1k v s = 15v a v = 1 r l = 2k and 10k c l = 4pf v out (mv) time (s) -40 -30 -20 -10 0 10 20 30 40 012345678910 a v = 1 r l = 2k and 10k c l = 4pf v s = 15v v s = 5v
isl28177 7 fn7859.2 april 5, 2012 applications information functional description the isl28177 is a low noise op amp fabricated in a 40v complementary bipolar di process designed for general purpose low power applications. it utilizes a super-beta npn input stage with input bias current cancellation for low input bias current and low input noise voltage. a comp limentary bipolar output stage enables high capacitive load drive without external compensation. operating voltage range the isl28177 is designed to operate over the 6v (3v) to 40v (20v) range. the common mode input voltage range extends to 2v from each rail, and the output voltage swings to 1.3v of each rail. input performance the super-beta npn input pair reduces input bias current while maintaining good frequency response, low input bias current and low noise. input bias cancellation circuits provide additional bias current reduction to <1na, and excellent temperature stabilization and low tcv os . input esd diode protection the input terminals (in+ and in-) have internal esd protection diodes to the positive and negati ve supply rails, series connected 500 ? current limiting resistors and an anti-parallel diode pair across the inputs (figure 21). the series resistors limit the high feed-through currents that can occur in pulse applications when the input dv/dt exceeds the 0.2v/s slew rate of the amplifier. without the series resistors, the input can forward-bias the anti-parallel diodes causing current to flow to the output, resulting in severe distortion and possible diode failure. figure 17 provides an example of distortion free large signal response using a 10v p-p input pulse with an input rise time of <1ns. the series resistors enable the inpu t differential voltage to be equal to the maximum power supply voltage (40v) without damage. in applications where one or both amplifier input terminals are at risk of exposure to high voltages beyond the power supply rails, current limiting resistors may be needed at the input terminal to limit the current through the power supply esd diodes to 20ma max. output current limiting the output current is internally limited to approximately 30ma at +25c and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. continuous operation under these conditio ns may degrade long term reliability. output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the isl28177 is immune to output phase reversal. figure 19. positive output overload response time figure 20. negative output overload response time typical performance curves v s = 15v, v cm = 0v, r l = open, unless otherwise specified. (continued) -2 0 2 4 6 8 10 12 14 16 -280 -240 -200 -160 -120 -80 -40 0 40 80 0 40 80 120 160 200 240 280 320 360 400 o u t p u t ( v ) i n p u t ( m v ) time (s) v s = 15v a v = 100 v in = 200mv p-p overdrive = 1v r l = 10k input output -16 -14 -12 -10 -8 -6 -4 -2 0 2 -80 -40 0 40 80 120 160 200 240 280 0 40 80 120 160 200 240 280 320 360 400 o u t p u t ( v ) i n p u t ( m v ) time (s) v s = 15v a v = 100 v in = 200mv p-p overdrive = 1v r l = 10k input output figure 21. input esd diode current limiting - + r l v in v out v+ v- 500 ? 500 ?
isl28177 8 fn7859.2 april 5, 2012 power dissipation it is possible to exceed the +150c maximum junction temperature under certain load and power supply conditions. it is therefore important to calculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions , or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1: where: ?pd maxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated using equation 2: where: ?t max = maximum ambient temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipa tion of 1 amplifier ?v s = total supply voltage ?i qmax = maximum quiescent supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application isl28177 spice model figure 22 shows the spice model schematic and figure 23 shows the net list for the spice model. the model is a simplified version of the actual device and simulates important ac and dc parameters. ac parameters incorporated into the model are: 1/f and flatband noise voltage, slew rate, cmrr, gain and phase. the dc parameters are, vos, i os , total supply current and output voltage swing. the model uses ty pical parameters given in the ?electrical specifications? table be ginning on page 3. the avol is adjusted for 140db with the dominant pole at 0.075hz. the cmrr is set 145db, f cm = 500khz. the input stage models the actual device to present an accurate ac representation. the model is configured for ambient temperature of +25c. figures 24 through 37 show the characterization vs simulation results for the noise voltage, closed loop gain vs frequency, small signal 0.1v step, large signal 5v step response, open loop gain phase, cmrr, unity gain frequency response vs c l and output voltage swing for 15v supplies. license statement the information in this spice model is protected under the united states copyright laws. intersil corporation hereby grants users of this macro-model hereto referred to as ?licensee?, a nonexclusive, nontransferable licen se to use this model as long as the licensee abides by the terms of this agreement. before using this macro-model, the licensee should read this license. if the licensee does not accept these terms, permission to use the model is not granted. the licensee may not sell, loan, re nt, or license the macro-model, in whole, in part, or in modified form, to anyone outside the licensee?s company. the licensee may modify the macro-model to suit his/her specific applications, and the licensee may make copies of this macro-model for use within their company only. this macro-model is provided ?as is, where is, and with no warranty of any kind either expressed or implied, including but not limited to any implied warranties of merchantability and fitness for a particular purpose.? in no event will intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. intersil reserves the right to make changes to the product and the macro-model without prior notice. t jmax t max ja xpd maxtotal + = (eq. 1) p d max v s i qmax v s ( - v outmax ) v outmax r l ---------------------------- + = (eq. 2)
isl28177 9 fn7859.2 april 5, 2012 2nd gain stage 2nd pole stage noise stage ref voltage common mode gain stage with zero correction current sources output stage input stage 1st gain stage mid supply 20 v++ v-- v++ 16 v-- 15 17 12 7 vc vin- 6 22 vin+ 8 1 2 3 14 19 21 vcm 11 13 vmid 18 10 23 24 vout 25 9 5 v+ 4 in+ v- 0 0 0 0 0 0 dx d3 isy 1.18e-3 isy 1.18e-3 q2 superb c2 2e-12 + - g12 gain = 1.11e-2 + - g12 r5 1 r5 1 dx d10 r14 1989.49546 r10 1 r10 1 r13 1989.49546 c9 10e-12 iee 200e-6 c8 10e-12 r16 1989.49546 r1 5e11 r12 1 r3 4.45e3 dx d9 + - g13 gain = 1.11e-2 g13 v6 0.18 c5 1e-9 c5 1e-9 v2 1.7 1.7 + - g3 gain = 4.712e-3 + - g3 gain = 4.712e-3 v1 0.07 v1 iee1 96e-6 dx d5 dx d5 dx d7 d7 c3 2e-12 v7 0.18 - + + - en - + + - c1 1.2e-12 - + + - eos gain = 1e-9 - + + - eos + - g2 gain = 0.06 + - g2 gain = 0.06 r9 1 r9 1 r19 5000 r2 5e11 v5 1.7 v5 + - g9 gain = 502.64e-6 + - g9 r8 2122.196e6 l1 318.31927e-6 l1 318.31927e-6 c4 1e-9 r7 2122.196e6 + - g1 gain = 0.06 + - g1 + - g5 gain = 0.1e-6 + - g5 gain = 0.1e-6 dn d1 + - g6 gain = 0.1e-6 + - g6 gain = 0.1e-6 q1 superb q4 cascode q4 dx d2 dx - + + - e2 gain = 1 - + + - e2 vos 150e-6 dx d6 d6 r11 1 + - g14 gain = 1.11e-2 g14 + - g8 gain = 502.64e-6 g8 ios 1e-9 + - g4 gain = 4.712e-3 + - g4 v3 1.7 v3 1.7 d x d8 r18 9e1 q3 mirror q3 mirror + - g10 gain = 502.64e-6 + - g10 r6 1 r6 1 dy d12 d12 c7 10e-12 dx d4 d4 r15 1989.49546 l2 318.31927e-6 318.31927e-6 r4 4.45e3 v4 1.7 v4 dy d11 d11 c6 10e-12 + - g7 gain = 502.64e-6 g7 r17 9e1 - + + - e1 gain = 1 e1 + - g11 gain = 1.11e-2 - g11 q5 cascode q5 figure 22. spice model schematic
isl28177 10 fn7859.2 april 5, 2012 *isl28177 macromodel **revision history: *revision a, lafontaine december 14, 2011 *model for noise, quiescent supply currents, *cmrr 145db, fcm=500khz, avol 140db *f=0.075hz sr = 0.2v/us, gbwp 600khz, *2nd pole 8mhz, output voltage clamp *and short ckt current limit. * *copyright 2011 by intersil corporation *refer to data sheet "license *statement", use of this model indicates *your acceptance with the terms and *provisions in the license statement. * *intended use: *this pspice macromodel is intended to give *typical dc and ac performance *characteristics under a wide range of *external circuit configurations using *compatible simulation platforms - such as *isim pe. * *device performance features supported by *this model *typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *open and closed loop i/o impedances *open loop gain and phase *closed loop bandwidth and frequency *response *loading effects on closed loop frequency *response *input noise terms including 1/f effects *slew rate *input and output headroom limits to i/o *voltage swing *supply current at nominal specified supply *voltages ** *device performance features not *supported by this model: *harmonic distortion effects *disable operation (if any) *thermal effects and/or over temperature *parameter variation *limited performance variation vs. supply *voltage is modeled *part to part performance variation due to *normal process parameter spread *any performance difference arising from *different packaging * source : *+input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | | .subckt isl28177 vin+ vin- v+ v- vout * source isl28177_spicemodel * *voltage noise e_en in+ vin+ 2 0 1 d_d1 1 2 dn v_v1 1 0 0.07 r_r19 2 0 5000 * *input stage i_ios in+ vin- dc 1e-9 c_c1 in+ vin- 1.2e-12 c_c2 0 vin- 2e-12 c_c3 0 in+ 2e-12 r_r1 vcm vin- 5e11 r_r2 in+ vcm 5e11 r_r3 6 v++ 4.45e3 r_r4 7 v++ 4.45e3 q_q1 4 vin- 3 superb q_q2 5 10 3 superb q_q3 v-- 3 9 mirror q_q4 6 8 4 cascode q_q5 7 8 5 cascode i_iee 3 v-- dc 200e-6 i_iee1 v++ 8 dc 96e-6 d_d2 8 9 dx e_eos 10 11 vc vmid 1e-9 v_vos 11 in+ 30e-6 * *1st gain stage g_g1 v++ 13 6 7 0.06 g_g2 v-- 13 6 7 0.06 r_r5 13 v++ 1 r_r6 v-- 13 1 v_v2 12 13 1.7 v_v3 13 14 1.7 d_d3 12 v++ dx d_d4 v-- 14 dx * *2nd gain stage g_g3 v++ 15 13 vmid 4.712e-3 g_g4 v-- 15 13 vmid 4.712e-3 r_r7 15 v++ 2122.196e6 r_r8 v-- 15 2122.196e6 v_v4 16 15 1.7 v_v5 15 17 1.7 d_d5 16 v++ dx d_d6 v-- 17 dx c_c4 15 v++ 1e-9 c_c5 v-- 15 1e-9 * *mid supply ref r_r9 vmid v++ 1 r_r10 v-- vmid 1 e_e1 v++ 0 v+ 0 1 e_e2 v-- 0 v- 0 1 i_isy v+ v- dc 1.18e-3 * *common mode gain stage with zero g_g5 v++ vc vcm vmid 0.1e-6 g_g6 v-- vc vcm vmid 0.1e-6 r_r11 vc 18 1 r_r12 19 vc 1 l_l1 18 v++ 318.31927e-6 l_l2 19 v-- 318.31927e-6 * *2nd pole stage g_g7 v++ 20 15 vmid 502.64e-6 g_g8 v-- 20 15 vmid 502.64e-6 g_g9 v++ 21 20 vmid 502.64e-6 g_g10 v-- 21 20 vmid 502.64e-6 r_r13 20 v++ 1989.49546 r_r14 v-- 20 1989.49546 r_r15 21 v++ 1989.49546 r_r16 v-- 21 1989.49546 c_c6 20 v++ 10e-12 c_c7 v-- 20 10e-12 c_c8 21 v++ 10e-12 c_c9 v-- 21 10e-12 * *output stage with correction current sources g_g11 vout v++ v++ 21 1.11e-2 g_g12 v-- vout 21 v-- 1.11e-2 g_g13 22 v-- vout 21 1.11e-2 g_g14 25 v-- 21 vout 1.11e-2 d_d7 21 23 dx d_d8 24 21 dx d_d9 v++ 22 dx d_d10 v++ 25 dx d_d11 v-- 22 dy d_d12 v-- 25 dy v_v6 23 vout 0.18 v_v7 vout 24 0.18 r_r17 vout v++ 9e1 r_r18 v-- vout 9e1 * .model superb npn + is=184e-15 bf=30e3 va=15 ik=70e-3 rb=50 + re=0.065 rc=35 cje=1.5e-12 cjc=2e-12 + kf=0 af=0 .model cascode npn + is=502e-18 bf=150 va=300 ik=17e-3 +rb=140 re=0.011 rc=900 cje=0.2e-12 +cjc=0.16e-12f kf=0 af=0 .model mirror pnp + is=4e-15 bf=150 va=50 ik=138e-3 rb=185 + re=0.101 rc=180 cje=1.34e-12 + cjc=0.44e-12 + kf=0 af=0 .model dn d(kf=6.69e-9 af=1) .model dx d(is=1e-12 rs=0.1) .model dy d(is=1e-15 bv=50 rs=1) .ends subckt isl28177 figure 23. spice net list
isl28177 11 fn7859.2 april 5, 2012 characterization vs simulation results figure 24. characterized input noise voltag e figure 25. simulated input noise voltage figure 26. characterized closed loop gain vs frequenc y figure 27. simulated closed loop gain vs frequency figure 28. characterized small signal transient response vs r l , v s = 0.9v, 2.5v figure 29. simulated small signal transient response v s = 15v 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o l t a g e ( n v / h z ) frequency (hz) i n p u t n o i s e c u r r e n t ( p a / h z ) 1 10 100 1000 10000 1 10 100 1000 10000 v s = 18v input noise voltage input noise current 0.1 1 10 100 1k 10k 100k frequency (hz) 1 10 100 1000 10000 input noise voltage v s = 15v i n p u t n o i s e v o l t a g e ( n v / h z ) -10 0 10 20 30 40 50 60 70 g a i n ( d b ) frequency (hz) 10 100 1k 10k 100k 1m 10m a cl = 1 a cl = 10 a cl = 1001 v s = 15v c l = 4pf v out = 50mv p-p r l = open a cl = 101 r f = 0, r g = r f = 100k ? , r g = 100 r f = 100k ? , r g = 1k r f = 100k ? , r g = 11k ? -10 0 10 20 30 40 50 60 70 g a i n ( d b ) frequency (hz) 10 100 1k 10k 100k 1m 10m a cl = 1 a cl = 10 a cl = 1001 v s = 15v c l = 4pf v out = 50mv p-p r l = open a cl = 101 r f = 100k ? , r g = 11k ? r f = 100k ? , r g = 1k r f = 100k ? , r g = 100 r f = 0, r g = v o u t ( m v ) time (s) -40 -30 -20 -10 0 10 20 30 40 012345678910 a v = 1 r l = 2k and 10k c l = 4pf v s = 5v v s = 15v v o u t ( m v ) time (s) -40 -30 -20 -10 0 10 20 30 40 012345678910 a v = 1 r l = 10k c l = 4pf
isl28177 12 fn7859.2 april 5, 2012 figure 30. characterized large signal transient response vs r l , v s =15v figure 31. simulated large signal transient response, v s =14v figure 32. simulated (design) open-loop gain, phase vs frequency figure 33. simulated (spice) open-loop gain, phase vs frequency figure 34. characterizedunity gain frequency response vs c l figure 35. simulated unity gain frequency response vs c l characterization vs simulation results (continued) v o u t ( v ) time (s) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 100 200 300 400 500 600 700 800 900 1k v s = 15v a v = 1 r l = 2k and 10k c l = 4pf v o u t ( v ) time (s) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 100 200 300 400 500 600 700 800 900 1k v s = 15v a v = 1 r l = 2k and 10k c l = 4pf g a i n ( d b ) , p h a s e ( ) frequency (hz) -40 -20 0 20 40 60 80 100 120 140 160 180 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 100m v s = 15v r l = 1m ? simulation gain phase g a i n ( d b ) , p h a s e ( ) frequency (hz) -40 -20 0 20 40 60 80 100 120 140 160 180 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 100m v s = 15v r l = 1m ? simulation gain phase normalized gain (db) frequency (hz) 10 100 1k 10k 100k 1m 10m -10 -8 -6 -4 -2 0 2 4 6 8 r l = 10k a v = +1 v s = 15v v out = 50mv p-p c l = 2200pf c l = 4pf c l = 1000pf c l = 4700pf c l = 10nf c l = 22nf normalized gain (db) frequency (hz) 10 100 1k 10k 100k 1m 10m -10 -8 -6 -4 -2 0 4 6 8 10 c l = 2200pf c l = 4pf c l = 1000pf c l = 4700pf c l = 10nf c l = 22nf 2
isl28177 13 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7859.2 april 5, 2012 for additional products, see www.intersil.com/product_tree . products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl28177 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear figure 36. simulated (spice) cmrr figure 37. simulated output voltage swing 15v characterization vs simulation results (continued) 0.01 0.1 1.0 10 100 1k 10k 100k 1m 10m 100m 1g 0 40 80 120 160 200 c m r r ( d b ) frequency (hz) -15 -10 -5 0 5 10 15 0 0.2 0.4 0.6 0.8 1.0 time (ms) 13.79v -13.8v voltage (v) revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change march 29, 2012 fn7859.2 changed note 1 in ?ordering information? on page 2 from: ?add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications.? to: ?please refer to tb347 for details on reel specifications.? listed out tape and reel parts individually in ?ordering information? on page 2 (ISL28177FBZ-t13, ISL28177FBZ-t7, ISL28177FBZ-t7a) january 5, 2012 fn7859.1 added spice model to data sheet. added esd ratings to description on page 1. october 31, 2011 fn7859.0 initial release
isl28177 14 fn7859.2 april 5, 2012 package outline drawing ( m8.15e) m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b?
isl28177 15 fn7859.2 april 5, 2012 package outline drawing p5.064a 5 lead small outline transistor plastic package rev 0, 2/10 dimension is exclusive of mold flash, protrusions or gate burrs. this dimension is measured at datum ?h?. package conforms to jedec mo-178aa. foot length is measured at reference to gauge plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 1.60 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 0.08-0.20 see detail x 1.45 max (0.60) 0-3 c b a d 3 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 5 2 4 5 5 end view plane

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